1. Field of the Invention
The present invention relates to a jitter counter, and to an optical disc apparatus using same.
2. Description of Related Art
Conventionally, in an optical disc apparatus that performs data recording/reproduction to and from an optical disc, a jitter counter that counts jitters of a binary-coded reproduction high-frequency signal (hereinafter, called a binary RF [Radio Frequency] signal) has been incorporated.
As documents that disclose examples of the prior art relating to a jitter counter, there are JP-A-2001-266359, JP-A-2005-18843, JP-A-2005-293812, and JP-A-2006-127620 (hereinafter, called as patent documents 1-4).
Indeed, an optical disc apparatus that incorporates a jitter counter can optimally adjust an offset amount of focus servo and offset servo, waveform equalization characteristics of an RF amplifier, and various characteristics of an optical pickup based on a jitter count value of a binary RF signal.
However, in the patent document 1, a jitter counter disclosed as an example of the prior art is so structured as to convert an output signal from a phase comparator into an absolute value, then, apply an A/D [analog/digital] conversion to the absolute value through an integrator, and carry out a jitter count. Therefore, a high-accurate analog integrator and an A/D converter are required.
Besides, the inventive apparatus described in the patent document 1 is so structured that it takes advantage of a characteristic that jitter shows a normal distribution, and counts the number of inversion positions of a binary signal using a clock that is slightly shifted in phase from a channel clock, and carries out the jitter count. Therefore, not only a PLL [Phase Locked Loop] circuit for signal reproduction but also a PLL circuit dedicated to the jitter count are additionally required.
The inventive apparatus described in the patent document 2 is SO structured that it applies sampling to a binary signal using an N-phase clock synchronized with a channel clock, and obtains information that has an N-time resolution in a time direction, and carries out the jitter count. Therefore, a VCO [Voltage Controlled Oscillator] dedicated to the jitter count is required, and a high-accurate N-phase clock layout is also required.
The inventive apparatus described in the patent document 3 is so structured that it counts a high-level width and a low-level width of a binary signal using a clock much faster than a channel clock, and carries out the jitter count. Therefore, a clock generation circuit that generates a clock much faster than the channel clock, and accordingly consumed power becomes large.
The inventive apparatus described in the patent document 4 is so structured that it delays a binary signal successively by reference periods of 1 T/S using an S-stage delay device, applies sampling to the delayed signals using a channel clock, and carries out the jitter count at high resolution. Therefore, large differences occur without an additional PLL circuit, and the apparatus cannot interact with various reproduction speeds. Besides, an additional PLL is required to carry out the jitter count to high accuracy.
As mentioned above, the above conventional jitter counters need a high-speed clock generation circuit, an A/D converter, a PLL circuit dedicated to the jitter count, a VCO and the like. Accordingly, the conventional jitter counters cannot be built in a digital system LSI at low cost.